VHDL and Verilog bus-functional model generator
TestBencher
is a system level test bench generator that creates bus functional models from
language independent timing diagrams. All the generated code is native VHDL,
Verilog, OpenVera, or SystemC so it can be simulated using any major
simulator.
TestBencher
automates the most tedious aspects of test bench development, allowing you to
focus on the design and operation of the test bench. This is accomplished by
representing each bus transaction graphically and then generating the code for
the transaction.
|
www.syncad.com
